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15.3.3.1 Idle-Line Multiprocessor Format
When UCMODEx = 01, the idle-line multiprocessor format is selected. Blocks of data are separated by an
idle time on the transmit or receive lines as shown in Figure 15-3. An idle receive line is detectedwhen 10
or more continuous ones (marks) are received after the one or two stop bits of a character. The baud rate
generator is switched off after reception of an idle line until the next start edge is detected. When an idle
line is detected the UCIDLE bit is set.
The first character received after an idle period is an address character. The UCIDLE bit is used as an
address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received
character is an address.The UCDORM bit is used to control data reception in the idle-line multiprocessor format. When
UCDORM = 1, all non-address characters are assembled but not transferred into the UCAxRXBUF, and
interrupts are not generated. When an address character is received, the character is transferred into
UCAxRXBUF, UCAxRXIFG is set, and any applicable error flag is set when UCRXEIE = 1. When
UCRXEIE = 0 and an address character is received but has a framing error or parity error, the character is
not transferred into UCAxRXBUF and UCAxRXIFG is not set.
If an address is received, user software can validate the address and must reset UCDORM to continue
receiving data. If UCDORM remains set, only address characters will be received. When UCDORM is
cleared during the reception of a character the receive interrupt flag will be set after the reception
completed. The UCDORM bit is not modified by the USCI hardware automatically.
For address transmission in idle-line multiprocessor format, a precise idle period can be generated by the
USCI to generate address character identifiers on UCAxTXD. The double-buffered UCTXADDR flag
indicates if the next character loaded into UCAxTXBUF is preceded by an idle line of 11 bits. UCTXADDR
is automatically cleared when the start bit is generated.15.3.5 IrDA Encoding and Decoding (phần này có thể giải thích rõ giùm em với ak)
When UCIREN is set the IrDA encoder and decoder are enabled and provide hardware bit shaping for
IrDA communication.
15.3.5.1 IrDA Encoding
The encoder sends a pulse for every zero bit in the transmit bit stream coming from the UART as shown
in Figure 15-7. The pulse duration is defined by UCIRTXPLx bits specifying the number of half clock
periods of the clock selected by UCIRTXCLK.
Figure 15-7. UART vs IrDA Data Format
To set the pulse time of 3/16 bit period required by the IrDA standard the BITCLK16 clock is selected with
UCIRTXCLK = 1 and the pulse length is set to 6 half clock cycles with UCIRTXPLx = 6 – 1 = 5.
When UCIRTXCLK = 0, the pulse length tPULSE is based on BRCLK and is calculated as follows:
UCIRTXPLx = t
PULSE × 2 × fBRCLK − 1
When the pulse length is based on BRCLK the prescaler UCBRx must to be set to a value greater or
equal to 5.
15.3.5.2 IrDA Decoding
The decoder detects high pulses when UCIRRXPL = 0. Otherwise it detects low pulses. In addition to the
analog deglitch filter an additional programmable digital filter stage can be enabled by setting UCIRRXFE.
When UCIRRXFE is set, only pulses longer than the programmed filter length are passed. Shorter pulses
are discarded. The equation to program the filter length UCIRRXFLx is:
UCIRRXFLx = (tPULSE − tWAKE) × 2 × fBRCLK − 4
Where,
t
PULSE = Minimum receive pulse width
t
WAKE = Wake time from any low power mode. Zero when MSP430 is in active mode.
15.3.3.1 Idle-Line Multiprocessor Format
When UCMODEx = 01, the idle-line multiprocessor format is selected. Blocks of data are separated by an
idle time on the transmit or receive lines as shown in Figure 15-3. An idle receive line is detectedwhen 10
or more continuous ones (marks) are received after the one or two stop bits of a character. The baud rate
generator is switched off after reception of an idle line until the next start edge is detected. When an idle
line is detected the UCIDLE bit is set.
The first character received after an idle period is an address character. The UCIDLE bit is used as an
address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received
character is an address.The UCDORM bit is used to control data reception in the idle-line multiprocessor format. When
UCDORM = 1, all non-address characters are assembled but not transferred into the UCAxRXBUF, and
interrupts are not generated. When an address character is received, the character is transferred into
UCAxRXBUF, UCAxRXIFG is set, and any applicable error flag is set when UCRXEIE = 1. When
UCRXEIE = 0 and an address character is received but has a framing error or parity error, the character is
not transferred into UCAxRXBUF and UCAxRXIFG is not set.
If an address is received, user software can validate the address and must reset UCDORM to continue
receiving data. If UCDORM remains set, only address characters will be received. When UCDORM is
cleared during the reception of a character the receive interrupt flag will be set after the reception
completed. The UCDORM bit is not modified by the USCI hardware automatically.
For address transmission in idle-line multiprocessor format, a precise idle period can be generated by the
USCI to generate address character identifiers on UCAxTXD. The double-buffered UCTXADDR flag
indicates if the next character loaded into UCAxTXBUF is preceded by an idle line of 11 bits. UCTXADDR
is automatically cleared when the start bit is generated.15.3.5 IrDA Encoding and Decoding (phần này có thể giải thích rõ giùm em với ak)
When UCIREN is set the IrDA encoder and decoder are enabled and provide hardware bit shaping for
IrDA communication.
15.3.5.1 IrDA Encoding
The encoder sends a pulse for every zero bit in the transmit bit stream coming from the UART as shown
in Figure 15-7. The pulse duration is defined by UCIRTXPLx bits specifying the number of half clock
periods of the clock selected by UCIRTXCLK.
Figure 15-7. UART vs IrDA Data Format
To set the pulse time of 3/16 bit period required by the IrDA standard the BITCLK16 clock is selected with
UCIRTXCLK = 1 and the pulse length is set to 6 half clock cycles with UCIRTXPLx = 6 – 1 = 5.
When UCIRTXCLK = 0, the pulse length tPULSE is based on BRCLK and is calculated as follows:
UCIRTXPLx = t
PULSE × 2 × fBRCLK − 1
When the pulse length is based on BRCLK the prescaler UCBRx must to be set to a value greater or
equal to 5.
15.3.5.2 IrDA Decoding
The decoder detects high pulses when UCIRRXPL = 0. Otherwise it detects low pulses. In addition to the
analog deglitch filter an additional programmable digital filter stage can be enabled by setting UCIRRXFE.
When UCIRRXFE is set, only pulses longer than the programmed filter length are passed. Shorter pulses
are discarded. The equation to program the filter length UCIRRXFLx is:
UCIRRXFLx = (tPULSE − tWAKE) × 2 × fBRCLK − 4
Where,
t
PULSE = Minimum receive pulse width
t
WAKE = Wake time from any low power mode. Zero when MSP430 is in active mode.
